On the speedup required for a multicast parallel packet switch

Author

Iyer, Sundar ; McKeown, Nick

Author_Institution

Comput. Syst. Lab., Stanford Univ., CA, USA

Volume

5

Issue

6

fYear

2001

fDate

6/1/2001 12:00:00 AM

Firstpage

269

Lastpage

271

Abstract

A parallel packet switch (PPS) is a switch in which the memories run slower than the line rate. Arriving packets are load-balanced packet-by-packet over multiple lower speed center stage packet switches. It is known that, for unicast traffic, a PPS can precisely emulate a FCFS output-queued (OQ) switch with a speedup of two and an OQ switch with delay guarantees with a speedup of three. In this paper we ask: is it possible for a PPS to emulate the behavior of an OQ multicast switch? The main result is that for multicast traffic an N-port PPS can precisely emulate a FIFO OQ switch with a speedup of S>2/spl radic/N+1, and a switch that provides delay guarantees with a speedup of S>2/spl radic/(2N)+2.

Keywords

delays; multicast communication; packet switching; queueing theory; FCFS output-queued switch; N-port PPS; OQ multicast switch; OQ switch; arriving packets; center stage packet switches; delay guarantees; load-balancing; multicast parallel packet switch; speedup; unicast traffic; Bandwidth; Computer architecture; Delay; Optical packet switching; Optical switches; Packet switching; Random access memory; Telecommunication traffic; Traffic control; Unicast;

fLanguage

English

Journal_Title

Communications Letters, IEEE

Publisher

ieee

ISSN

1089-7798

Type

jour

DOI

10.1109/4234.929609

Filename

929609