The evolution of instruction sequencing

Author

Krick, Robert F. ; Dollas, Apostolos

Author_Institution

Intel Corp., Hillsboro, OR, USA

Volume

24

Issue

4

fYear

1991

fDate

4/1/1991 12:00:00 AM

Firstpage

5

Lastpage

15

Abstract

The three distinct phases that constitute the sequencing of an instruction are determining the memory address that contains the instruction, fetching the instruction from memory, and executing the instruction. The evolution of instruction sequencing is traced, with attention focused on the influence of the available technology on the minimum time required for each of these phases and the resulting design decisions. Rather than absolute system performance. the interrelationship of these critical parameters is examined. Memory bandwidth, instruction buffers, caches, and the impact of reduced-instruction-set computers (RISCs) are discussed. Recent innovations are described, and the options and constraints that designers face with respect to future developments are evaluated.<>

Keywords

instruction sets; reduced instruction set computing; caches; critical parameters; design decisions; instruction buffers; instruction sequencing; memory address; memory bandwidth; reduced-instruction-set computers; Bandwidth; Bipolar transistors; Context modeling; Interleaved codes; Magnetic cores; Random access memory; Semiconductor memory; System performance; Tellurium; Terminology;

fLanguage

English

Journal_Title

Computer

Publisher

ieee

ISSN

0018-9162

Type

jour

DOI

10.1109/2.76259

Filename

76259