Low Specific on-Resistance Power MOS Transistor With Multilayer Carrier Accumulation Breaks the Limit Line of Silicon

In this paper, a new power metal-oxide-semiconductor field-effect transistor (MOSFET) with a FS surface to reduce the specific on-resistance R_on,sp is proposed. Semi-insulating polycrystalline silicon (SIPOS) is deposited over a thin oxide layer. Drift-region concentration is higher in the proposed device than that of conventional lateral double-diffused MOS (LDMOS), and its structure with SIPOS is compared at the same breakdown voltage Bv. In the proposed MOSFET, the effect of electric-field modulation is improved, when compared with an accumulation LDMOS transistor (ALDMOST) due to a complete 3-D reduced surface-field effect. An extra multilayer majority carrier is introduced on the sidewalls of the trench, which reduces R_on,sp of the drift region. This indicates that the ideal silicon limit of the tradeoff of Bv and R_on,sp has been broken due to the lowest R_on,sp value in the proposed MOSFET. In the proposed MOSFET, R_on,sp (i.e., 13.5 mΩ·cm²) and Bv (i.e., 440 V) are improved greatly, when compared with the ALDMOST (i.e., with an R_on,sp of 26 mΩ·cm² and Bv of 400 V) and a superjunction structure (i.e., with an R_on,sp of 98 mΩ·cm² and Bv of 410 V).