• DocumentCode
    1509902
  • Title

    A fast pump-down VBB generator for sub-1.5-V DRAMs

  • Author

    Min, Kyeong-Sik ; Chung, Jin-Yong

  • Author_Institution
    Adv. Memory Design Dept., Hyundai Electron. Inc. Co. Ltd., Cheongju-si, South Korea
  • Volume
    36
  • Issue
    7
  • fYear
    2001
  • fDate
    7/1/2001 12:00:00 AM
  • Firstpage
    1154
  • Lastpage
    1157
  • Abstract
    Based on the study about the previously developed VBB generators, a fast pump-down and high-efficiency VBB generator with a cross-coupled hybrid pumping circuit 2 (CHPC2) is presented in this paper. CHPC2 takes only the advantages from the previous generators, eliminating the disadvantages. CHPC2 shows a |VBB|/VCC as large as 98% even at low VCC =0.9 V, strongly ensuring that it is suitable at sub-1.5-V DRAM applications. Moreover, CHPC2 exhibits a better pumping efficiency and a larger pumping current over the previous ones with a wide range of the load resistance at VCC=1.2 V
  • Keywords
    CMOS memory circuits; DRAM chips; reference circuits; signal generators; voltage multipliers; 0.9 to 1.5 V; DRAMs; LV memory circuit; back bias voltage generator; charge pump; cross-coupled hybrid pumping circuit; dynamic RAM; fast pump-down VBB generator; high-efficiency VBB generator; Capacitance; Circuits; Clocks; Degradation; Helium; Hybrid power systems; MOS devices; Random access memory; Switches; Voltage control;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/4.933476
  • Filename
    933476
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1509902