A multiple clocking scheme for low-power RTL design

This paper presents a resource allocation technique to design low-power register-transfer-level datapaths. The basis of this technique is to use a multiple clocking scheme of n nonoverlapping clocks, by dividing the frequency f of a single clock into n cycles, to partition the circuit into n disjoint modules and assign each module to a distinct clock, and to operate each module only during its corresponding duty cycle, thus clocking each module by a frequency f/n to reduce power. However, the overall effective frequency of the circuit remains f, i.e., the single clock frequency. Further power reduction is also obtained by tradeoffs between voltage, power, and delay across multiple clock partitions. Power savings up to 50% of the proposed multiple clocking scheme in comparison to single gated clock designs are also reported.