DocumentCode
1511921
Title
Path metric memory management for minimising interconnections in Viterbi decoders
Author
Kim, S.-Y. ; Kim, H. ; Park, I.-C.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
Volume
37
Issue
14
fYear
2001
fDate
7/5/2001 12:00:00 AM
Firstpage
925
Lastpage
926
Abstract
To simplify the interconnection between processing elements and path metric memory banks in Viterbi decoders, a new path metric update scheme is proposed based on two techniques, named swapped state grouping and swapped computing. The proposed scheme leads to a simple interconnection consisting of 2×2 switches
Keywords
CMOS digital integrated circuits; Viterbi decoding; digital signal processing chips; integrated circuit interconnections; minimisation; storage management; Viterbi decoders; interconnections minimisation; path metric memory management; path metric update scheme; swapped computing; swapped state grouping;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20010617
Filename
935145
Link To Document