Multiple twisted dataline techniques for multigigabit DRAMs

Author

Min, Dong-Sun ; Langer, Dietrich W.

Author_Institution

Dept. of Electr. Eng., Pittsburgh Univ., PA, USA

Volume

34

Issue

6

fYear

1999

fDate

6/1/1999 12:00:00 AM

Firstpage

856

Lastpage

865

Abstract

To provide reliable scaled DRAMs, new multiple twisted dataline techniques are proposed and analyzed. Their effectiveness in reducing both the bitline (BL) and wordline (WL) coupling noises in scaled DRAM´s was evaluated by means of soft-error-rate measurements on 256-Mbit and 1-Gbit DRAM test chips. At the 1-Gbit level of integration, in our proposed scheme-compared to the conventional twisted bitline (TBL) scheme-the chip area penalty due to twisting is reduced by 66% and the BL coupling noise is reduced by 45%. At the 256-Mbit level, when the proposed technique is applied to both the BL and WL structures, we achieved a 64% coupling noise reduction compared to the conventional TBL and WL schemes. Faster data access time can also be expected when the proposed technique is applied to BL and/or WL structures

Keywords

CMOS memory circuits; DRAM chips; crosstalk; integrated circuit interconnections; integrated circuit layout; integrated circuit noise; 256 Mbit to 1 Gbit; bitline coupling noise; dynamic RAM; multigigabit DRAMs; multiple twisted dataline techniques; reliable scaled DRAMs; soft-error-rate measurements; wordline coupling noise; Crosstalk; Integrated circuit interconnections; Integrated circuit noise; Noise measurement; Noise reduction; Random access memory; Research and development; Semiconductor device noise; Semiconductor memory; Signal to noise ratio;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.766820

Filename

766820