A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS

Author

Zhu, Yan ; Chan, Chi-Hang ; Chio, U-Fat ; Sin, Sai-Weng ; Seng-Pan U ; Martins, Rui Paulo ; Maloberti, Franco

Author_Institution

VLSI Lab., Univ. of Macau, Macao, China

Volume

45

Issue

6

fYear

2010

fDate

6/1/2010 12:00:00 AM

Firstpage

1111

Lastpage

1121

Abstract

A 1.2 V 10-bit 100 MS/s Successive Approximation (SA) ADC is presented. The scheme achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Moreover, the use of a common-mode based charge recovery switching method reduces the switching energy and improves the conversion linearity. A variable self-timed loop optimizes the reset time of the preamplifier to improve the conversion speed. Measurement results on a 90 nm CMOS prototype operated at 1.2 V supply show 3 mW total power consumption with a peak SNDR of 56.6 dB and a FOM of 77 fJ/conv-step.

Keywords

CMOS integrated circuits; preamplifiers; CMOS prototype; common-mode based charge recovery switching; conversion linearity; on-chip reference generator; power 3 mW; power consumption; preamplifier; reference-free SAR ADC; size 90 nm; static power dissipation; successive approximation ADC; switching energy; variable self-timed loop; voltage 1.2 V; word length 10 bit; Digital video broadcasting; Energy consumption; Laboratories; Linearity; Pipelines; Power dissipation; Power generation; Silicon compounds; Very large scale integration; Voltage; Charge-recovery; reference-free; switched technique;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2010.2048498

Filename

5482529