Fully differential switched-current memory cell with low charge-injection errors

A fully differential switched-current memory cell with low charge-injection errors is proposed. The cell uses constant-voltage switching to obtain signal-independent charge injection, which is rejected using suitable differential structures. The cell is designed using a 0.35 μm digital CMOS process. Simulation results of the cell with a clock frequency of 13 MHz and with input signal amplitudes nearly as high as the bias current (600 μA) show a total harmonic distortion of -66 dB, a current transfer error of less than 0.4% and a signal-to-noise ratio of 60 dB