• DocumentCode
    1513832
  • Title

    RAGS-real-analysis ALAP-guided synthesis

  • Author

    Rhodes, David L. ; Wolf, Wayne

  • Author_Institution
    Dept. of Electr. Eng., Princeton Univ., NJ, USA
  • Volume
    20
  • Issue
    8
  • fYear
    2001
  • fDate
    8/1/2001 12:00:00 AM
  • Firstpage
    931
  • Lastpage
    941
  • Abstract
    A new technique for single-bus heterogeneous system scheduling and hardware-software codesign is presented. This technique addresses challenging real-time problem domains (e.g., multirate periodic dependent tasks) for preemptive target systems including real-time operating system overheads and communication contention along with proper protocol handling. Such realistic system attributes are often times ignored in scheduling and codesign efforts, but are addressed here using a novel “real-analysis” approach. This technique foregoes the usual list- or cluster-oriented scheduling techniques for an as-late-as-possible (ALAP) guided iterative improvement procedure. A detailed system simulation is used at the scheduling level, which in turn is used as the core of the overall cosynthesis. Since an accurate simulation is the basis for the schedule feasibility check, separate verification steps become unnecessary. In addition to using real analysis as part of the scheduling, several other unique or unusual features are employed including the use of ALAP in heterogeneous scheduling, recursive search level at a time, allowing backtracking while maintaining polynomial execution time, as well as others. This framework appears to be unique in its ability to address the allocation/scheduling and codesign of heterogeneous systems, which, in particular, employ arbitrated buses for intertask communication
  • Keywords
    hardware-software codesign; processor scheduling; real-time systems; system buses; RAGS; hardware-software codesign; intertask communication; iterative method; multirate periodic dependent task; processing element; protocol; real-analysis ALAP-guided synthesis; real-time operating system; single bus heterogeneous system scheduling; system simulation; Communication system software; Hardware; Helium; Integrated circuit interconnections; Modeling; Operating systems; Polynomials; Processor scheduling; Protocols; Real time systems;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.936375
  • Filename
    936375