DocumentCode
1513895
Title
25-nm p-channel vertical MOSFETs with SiGeC source-drains
Author
Yang, Min ; Chang, Chia-Lin ; Carroll, Malcolm ; Sturm, J.C.
Author_Institution
Dept. of Electr. Eng., Princeton Univ., NJ, USA
Volume
20
Issue
6
fYear
1999
fDate
6/1/1999 12:00:00 AM
Firstpage
301
Lastpage
303
Abstract
The scaling of vertical p-channel MOSFETs with the source and drain doped with boron during low temperature epitaxy is limited by the diffusion of boron during subsequent side wall gate oxidation. By introducing thin SiGeC layers in the source and drain regions, this diffusion has been suppressed, enabling for the first time the scaling of vertical p-channel MOSFETs to under 100 nm in channel length to be realized. Device operation with a channel length down to 25 nm has been achieved.
Keywords
MOSFET; semiconductor growth; vapour phase epitaxial growth; 25 nm; SiGeC; VPE; channel length; low temperature epitaxy; p-channel vertical MOSFETs; scaling; side wall gate oxidation; Atom optics; Boron; Doping; Epitaxial growth; Epitaxial layers; Lithography; MOSFET circuits; Oxidation; Substrates; Temperature;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/55.767105
Filename
767105
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