High-voltage drain extended MOS transistors for 0.18-μm logic CMOS process

Author

Mitros, Jozef C. ; Tsai, Chin-Yu ; Shichijo, Hisashi ; Kunz, Keith ; Morton, Alec ; Goodpaster, Doug ; Mosher, Dan ; Efland, Taylor R.

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

Volume

48

Issue

8

fYear

2001

fDate

8/1/2001 12:00:00 AM

Firstpage

1751

Lastpage

1755

Abstract

Complementary high-voltage drain extended (DE) MOS transistors were implemented into Texas Instruments´ state-of-the-art production advanced analog and digital 1.5-1.8 V CMOS technology. These transistors allow for 5-V drain operating voltage using the core gate oxide and have drain breakdown voltages BV_dss>10 V. Experimental results along with Suprem4 and MEDICI simulation results are presented to explain their operation. The novel p-channel transistors use an isolated compensated p-well as a drain extension. The n-channel version uses n-well as a drain extension. Experimental test results of I_ds(V_ds,V_gs), I_gs(V_ds), and BV(L) plots demonstrate DE-MOS performance. The work was focused on performance optimization with zero process modification and hence no cost adder

Keywords

CMOS logic circuits; VLSI; isolation technology; power MOSFET; power integrated circuits; semiconductor device breakdown; semiconductor device models; 0.18 micron; 5 V; MEDICI simulation; Suprem4 simulation; VLSI; core gate oxide; drain breakdown voltage; drain potential contours; high-voltage drain extended MOST; isolated compensated p-well; logic CMOS process; mixed mode technology; n-channel version; p-channel transistors; performance optimization; shallow trench isolation; zero process modification; Breakdown voltage; CMOS logic circuits; CMOS technology; Decision support systems; Instruments; Isolation technology; MOSFETs; Medical simulation; Production; Transistors;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.936703

Filename

936703