• DocumentCode
    1515948
  • Title

    PAUC: Power-Aware Utilization Control in Distributed Real-Time Systems

  • Author

    Wang, Xiaorui ; Fu, Xing ; Liu, Xue ; Gu, Zonghua

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Univ. of Tennessee, Knoxville, TN, USA
  • Volume
    6
  • Issue
    3
  • fYear
    2010
  • Firstpage
    302
  • Lastpage
    315
  • Abstract
    CPU utilization control has recently been demonstrated to be an effective way of meeting end-to-end deadlines for distributed real-time systems running in unpredictable environments. However, current research on utilization control focuses exclusively on task rate adaptation, which cannot effectively handle rate saturation and discrete task rates. Since the CPU utilization contributed by a real-time periodic task is determined by both its rate and execution time, CPU frequency scaling can be used to adapt task execution times for power-efficient utilization control. In this paper, we present PAUC, a two-layer coordinated CPU utilization control architecture. The primary control loop uses frequency scaling to locally control the CPU utilization of each processor, while the secondary control loop adopts rate adaptation to control the utilizations of all the processors at the cluster level on a finer timescale. Both the two control loops are designed and coordinated based on well-established control theory for theoretically guaranteed control accuracy and system stability. Empirical results on a physical testbed demonstrate that our control solution outperforms a state-of-the-art utilization control algorithm by having more accurate control and less power consumption. Extensive simulation results also show that our solution can significantly improve the feasibility of utilization control.
  • Keywords
    data communication equipment; distributed control; distributed processing; embedded systems; power aware computing; CPU frequency scaling; CPU utilization control; PAUC; control theory; distributed real-time systems; power-aware utilization control; primary control loop; processor; real-time embedded systems; secondary control loop; system stability; two-layer coordinated CPU utilization control architecture; Feedback control; power-aware computing; real-time embedded systems; utilization control;
  • fLanguage
    English
  • Journal_Title
    Industrial Informatics, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1551-3203
  • Type

    jour

  • DOI
    10.1109/TII.2010.2051232
  • Filename
    5484607