• DocumentCode
    1522532
  • Title

    Development of robust interconnect model based on design of experiments and multiobjective optimization

  • Author

    Zhang, Qiang ; Liou, Juin J. ; McMacken, J. ; Thomson, J. ; Layman, P.

  • Author_Institution
    Microelectron. Group, Central Florida Univ., Orlando, FL, USA
  • Volume
    48
  • Issue
    9
  • fYear
    2001
  • fDate
    9/1/2001 12:00:00 AM
  • Firstpage
    1885
  • Lastpage
    1891
  • Abstract
    When designing an integrated circuit, it is important to take into consideration random variations arising from process variability. Traditional optimization studies on VLSI interconnect attempt to find the deterministic optimum of a cost function but do not take into account the effect of these random variations on the objective. We have developed an effective methodology based on TCAD simulation and design of experiments to optimize interconnect including the effects of process variations. The aim of the study is to search for optimum designs that both meet the performance specification and are robust with respect to process variations. A multiobjective optimization technique known as Normal Boundary Intersection is used to find evenly-spaced tradeoff points on the Pareto curve. Designers can then select designs from the curve without using arbitrary weighting parameters. The proposed methodology was applied to a 0.12 μm CMOS technology; optimization results are discussed and verified using Monte Carlo simulation
  • Keywords
    CMOS integrated circuits; Monte Carlo methods; Pareto distribution; VLSI; circuit optimisation; design of experiments; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; technology CAD (electronics); 0.12 micron; CMOS integrated circuit design; Monte Carlo simulation; Pareto curve; TCAD; VLSI interconnect model; cost function; design of experiments; multiobjective optimization; normal boundary intersection; process variations; CMOS technology; Circuit simulation; Computational modeling; Cost function; Design optimization; Integrated circuit interconnections; Noise robustness; Optimization methods; Pareto optimization; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.944173
  • Filename
    944173