Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA

Author

Barranco, Francisco ; Tomasi, Matteo ; Diaz, Javier ; Vanegas, Mauricio ; Ros, Eduardo

Author_Institution

Dept. of Comput. Archit. & Technol., Univ. of Granada, Granada, Spain

Volume

20

Issue

6

fYear

2012

fDate

6/1/2012 12:00:00 AM

Firstpage

1058

Lastpage

1067

Abstract

The proposed work presents a highly parallel architecture for motion estimation. Our system implements the well-known Lucas and Kanade algorithm with the multi-scale extension for the computation of large motion estimations in a dedicated device [field-programmable gate array (FPGA)]. Our system achieves 270 frames per second for a 640 × 480 resolution in the best case of the mono-scale implementation and 32 frames per second for the multi-scale one, fulfilling the requirements for a real-time system. We describe the system architecture, address the evaluation of the accuracy with well-known benchmark sequences (including a comparative study), and show the main hardware resources used.

Keywords

field programmable gate arrays; image resolution; image sequences; motion estimation; parallel architectures; FPGA; Kanade algorithm; Lucas algrithm; field-programmable gate array; hierarchical optical flow estimation; motion estimation; multiscale extension; parallel architecture; Accuracy; Adaptive optics; Computer architecture; Estimation; Hardware; Optical imaging; Pixel; Field-programmable gate arrays (FPGAs); machine vision; real time systems; reconfigurable architectures;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2011.2145423

Filename

5772045