Test pattern generation for droop faults

In nanometer ICs, when several transistors in physical proximity switch within the same clock cycle, a substantial power supply drop, known as droop, may occur because of concurrent load on a via of the power grid. Transistors may slow down because of lower supply voltage. Modelling of such timing faults, termed as droop faults, and their impact on the functionality and timing behaviour of the circuit are yet to be fully understood. In this study, a simple automatic test pattern generation (ATPG) based procedure for stuck-at faults has been adapted to test droop faults. For validation of the methodology in combinational circuits and full scan sequential circuits, a set of appropriate clusters of gates is selected to cover potential droop-prone regions in a circuit. Experimental results on ISCAS-85 and ISCAS-89 benchmark circuits reveal that a very high droop fault coverage can be obtained by applying a short sequence of test vectors.