• DocumentCode
    1527114
  • Title

    Novel serial-parallel multipliers

  • Author

    Saleh, H.I. ; Khalil, A.H. ; Ashour, M.A. ; Salama, A.E.

  • Author_Institution
    NCRRT, Cairo, Egypt
  • Volume
    148
  • Issue
    4
  • fYear
    2001
  • fDate
    8/1/2001 12:00:00 AM
  • Firstpage
    183
  • Lastpage
    189
  • Abstract
    New designs of serial-parallel multipliers based on the modified Booth and multi-bit recoding algorithms are introduced. Using recoding for the parallel operand, two proposed systolic multipliers have been introduced to build structures having n/2 and n/3 cells. The proposed serial-parallel multipliers are compared with other structures on the basis of multiplication time, area, and complexity. By using multi-bit overlapped recoding of the multiplier operand, the multiplier operates at twice the speed of the existing designs and has a much lower AT2 complexity
  • Keywords
    digital arithmetic; multiplying circuits; systolic arrays; modified Booth algorithm; multi-bit overlapped recoding; serial-parallel multiplier; systolic multiplier;
  • fLanguage
    English
  • Journal_Title
    Circuits, Devices and Systems, IEE Proceedings -
  • Publisher
    iet
  • ISSN
    1350-2409
  • Type

    jour

  • DOI
    10.1049/ip-cds:20010338
  • Filename
    948389
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1527114