Robust design of low power CMOS analogue integrated circuits

As feature sizes move into the deep submicron ranges and power supply voltages are reduced, the effect of both device mismatch and inter-die process variations on the performance and reliability of analogue integrated circuits is magnified. The statistical MOS (SMOS) model accounts for both inter-die and intra-die variations. A low power analogue CMOS square-law cell, and a new transconductor and multiplier using this cell as the main building block, are presented in the paper. The paper focuses on the robust design of the transconductor and multiplier circuits. The circuits operate in the saturation region with fully balanced input signals. Initial circuit simulation results are given. Response surface methodology and design of experiment techniques were used as statistical VLSI design techniques combined with the SMOS model. Device size optimisation and yield enhancement are demonstrated