DocumentCode
1527146
Title
SRAM transparent testing methodology using dynamic power supply current
Author
Kim, H.-S. ; Yoon, D.-H. ; Kang, S.
Author_Institution
Dept. of Electr. & Comput. Eng., Yonsei Univ., Seoul, South Korea
Volume
148
Issue
4
fYear
2001
fDate
8/1/2001 12:00:00 AM
Firstpage
217
Lastpage
222
Abstract
A new transparent testing methodology using dynamic power supply current is proposed which is much simpler than traditional transparent testing algorithms. It employs the dynamic power supply current instead of making signatures so that it does not need the extra steps and hardware to generate a signature. The paper describes how to convert a March algorithm to a transparent one and how to cover the fault models considered. The transformed algorithm is much simpler and test time can be greatly reduced. In addition, it can detect extra faults that the original algorithm cannot. The whole BIST architecture is described, together with a new peak current detector
Keywords
SRAM chips; built-in self test; fault diagnosis; integrated circuit testing; BIST architecture; March algorithm; SRAM; dynamic power supply current; fault models; peak current detector; test time; transparent testing methodology;
fLanguage
English
Journal_Title
Circuits, Devices and Systems, IEE Proceedings -
Publisher
iet
ISSN
1350-2409
Type
jour
DOI
10.1049/ip-cds:20010337
Filename
948394
Link To Document