• DocumentCode
    1528374
  • Title

    A &thetas;(1) algorithm for modulo addition

  • Author

    Elleithy, Khaled M. ; Bayoumi, Magdy A.

  • Author_Institution
    Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA
  • Volume
    37
  • Issue
    5
  • fYear
    1990
  • fDate
    5/1/1990 12:00:00 AM
  • Firstpage
    628
  • Lastpage
    631
  • Abstract
    A θ(1) algorithm for large modulo addition for architectures based on the residue number (RNS) is proposed. The addition is done in a fixed number of stages which does not depend on the size of the modulus. The proposed modulo adder is much faster than previous adders and more area efficient. The implementation of the adder is modular and is based on simple cells, which leads to efficient VLSI realization
  • Keywords
    VLSI; adders; digital arithmetic; &thetas;(1) algorithm; area efficient; efficient VLSI realization; modulo adder; modulo addition; residue number; Adders; Arithmetic; Circuits and systems; Computer architecture; Digital filters; Fast Fourier transforms; Filtering; Signal processing algorithms; Table lookup; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0098-4094
  • Type

    jour

  • DOI
    10.1109/31.55001
  • Filename
    55001
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1528374