DocumentCode
1528523
Title
Gasping the impact of on-chip inductance
Author
Massoud, Yehia ; Ismail, Yehea
Volume
17
Issue
4
fYear
2001
fDate
7/1/2001 12:00:00 AM
Firstpage
14
Lastpage
21
Abstract
The rapid advancements in process technology and heightening market pressures for functional integration are resulting in large VLSI chips operating at steadily increasing frequencies. The number of long global wires per chip has been continuously increasing with time. These wires carry high-frequency currents and have low resistance. This low resistance is due to the use of thick and wide interconnects at higher metal layers. Additionally, superior conducting materials such as copper have been introduced in order to keep the resistance and the RC delay of global lines small. These factors have led to a continuous increase in the importance of inductance, which has emerged as a standard factor that designers must take into consideration when designing high-performance chips in deep-submicron technologies. In this paper, the authors briefly discuss the importance, physical nature, effects, and extraction issues of on-chip inductance. Understanding the effects of on-chip inductance in high-speed integrated circuits is crucial to high-performance design
Keywords
VLSI; crosstalk; delay estimation; digital integrated circuits; high-speed integrated circuits; inductance; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; RC delay; VLSI chips; deep-submicron technologies; high-performance chips; high-performance design; high-speed integrated circuits; inductance extraction; inductance modelling; interconnects; onchip inductance; Conducting materials; Copper; Delay lines; Frequency; High speed integrated circuits; Inductance; Integrated circuit interconnections; Integrated circuit technology; Very large scale integration; Wires;
fLanguage
English
Journal_Title
Circuits and Devices Magazine, IEEE
Publisher
ieee
ISSN
8755-3996
Type
jour
DOI
10.1109/101.950046
Filename
950046
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