DocumentCode
1529940
Title
Novel Capacitorless 1T-DRAM Cell for 22-nm Node Compatible With Bulk and SOI Substrates
Author
Rodriguez, Noel ; Cristoloveanu, Sorin ; Gamiz, Francisco
Author_Institution
Dept. of Electron., Univ. of Granada, Granada, Spain
Volume
58
Issue
8
fYear
2011
Firstpage
2371
Lastpage
2377
Abstract
A new concept of multibody single-transistor dynamic-random-access-memory cell fully compatible with both standard bulk and silicon-on-insulator substrates is presented. Its novelty comes from the juxtaposition of two silicon films with opposed doping polarities (i.e., a p-n junction), which define a body partitioning for hole storage and current sense. The charge accumulated in the top body controls the current flowing through the bottom body. The scalability is ensured due to the suppression of the supercoupling effect, thus allowing the coexistence of electrons and holes in very thin transistors. Numerical simulations of electrostatics and dynamic operation show how the transient response of this device can be used for dynamic-memory applications, achieving attractive performance in terms of state discrimination and retention time in very scaled devices.
Keywords
random-access storage; silicon-on-insulator; substrates; SOI substrates; Si; capacitorless 1T-DRAM cell; current sense; dynamic-memory application; hole storage; multibody single-transistor dynamic-random-access-memory cell; silicon films; silicon-on-insulator substrates; transient response; Charge carrier processes; Computer architecture; Doping; Logic gates; MOSFET circuits; Microprocessors; Substrates; Advanced random-access memory (A-RAM); MOSFET; capacitorless; floating body (FB); silicon on insulator (SOI); simulation; single-transistor dynamic random-access memory (1T-DRAM); zero-capacitor random-access memory (Z-RAM);
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2011.2147788
Filename
5779718
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