• DocumentCode
    1532000
  • Title

    Exploiting instruction- and data-level parallelism

  • Author

    Espasa, Roger ; Valero, Mateo

  • Author_Institution
    Univ. Politecnica de Catalunya, Barcelona, Spain
  • Volume
    17
  • Issue
    5
  • fYear
    1997
  • Firstpage
    20
  • Lastpage
    27
  • Abstract
    Simultaneous multithreaded vector architectures combine the best of data-level and instruction-level parallelism and perform better than either approach could separately. Our design achieves performance equivalent to executing 15 to 26 scalar instructions/cycle for numerical applications
  • Keywords
    parallel architectures; performance evaluation; vector processor systems; data-level parallelism; instruction-level parallelism; performance; simultaneous multithreaded; vector architectures; Clocks; Computer aided instruction; Delay; Multithreading; Out of order; Parallel processing; Random access memory; Registers; Wire; Yarn;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/40.621210
  • Filename
    621210
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1532000