DocumentCode
1535566
Title
The 68040 32-b monolithic processor
Author
Anderson, Donnie ; Dewitt, B. Chris ; Eisele, Renny L. ; Gallup, Michael G. ; Ho, Ying-Wai ; McMahan, Steven C. ; Marquette, Daniel ; Martin, Bradley ; Scheuer, Kenneth C. ; Sood, Lal C. ; Spohrer, Thomas S.
Author_Institution
Motorola Inc., Austin, TX, USA
Volume
25
Issue
5
fYear
1990
fDate
10/1/1990 12:00:00 AM
Firstpage
1178
Lastpage
1189
Abstract
A 32-b single-chip processor has been developed that is user object-code compatible with members of the 68000 processor family. The 14-4-mm×15.5-mm device contains over 1.2 million transistors and is fabricated with a double-layer-metal CMOS process. The processor integrates three major functional units: an integer processor: a floating-point processor; and a Harvard-style memory unit. Each major unit is described, and the implementation techniques that were employed and selected circuit issues that were confronted in the design are discussed
Keywords
CMOS integrated circuits; microprocessor chips; 32 bit; Harvard-style memory unit; Motorola; double-layer-metal CMOS process; floating-point processor; integer processor; monolithic processor; single-chip processor; CMOS process; Clocks; Delay lines; Frequency; Helium; Memory management; Phase detection; Phase locked loops; System buses; Timing;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.62140
Filename
62140
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