• DocumentCode
    1535687
  • Title

    Path delay fault diagnosis in combinational circuits with implicit fault enumeration

  • Author

    Pant, Pankaj ; Hsu, Yuan-Chieh ; Gupta, Sandeep K. ; Chatterjee, Abhijit

  • Author_Institution
    Alpha Dev. Group, Compaq Comput. Corp., Houston, TX, USA
  • Volume
    20
  • Issue
    10
  • fYear
    2001
  • fDate
    10/1/2001 12:00:00 AM
  • Firstpage
    1226
  • Lastpage
    1235
  • Abstract
    A new methodology involving effect-cause analysis has been demonstrated for the diagnosis of path delay faults. The paper illustrates a structural representation, called the suspect circuit, of all the possible path delay faults in a faulty circuit. This representation has been used to design efficient algorithms that enable us to manipulate the suspect faults without having to enumerate them explicitly. Procedures for removing fault-free paths from the list of suspect faults have been implemented to improve the diagnostic resolution. Moreover, efficient data structures are used to complement the procedures and reduce the memory footprint of the algorithms. Results indicate that the diagnostic resolution obtained is very high and includes all possible causes of the observed delay faults
  • Keywords
    automatic test pattern generation; combinational circuits; delays; fault diagnosis; logic testing; combinational circuits; data structures; diagnostic resolution; effect-cause analysis; fault-free paths; implicit fault enumeration; memory footprint; observed delay faults; path delay fault diagnosis; structural representation; suspect circuit; Algorithm design and analysis; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Delay effects; Fault diagnosis; Predictive models; Silicon; Timing;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.952739
  • Filename
    952739