• DocumentCode
    1535890
  • Title

    20Gbit/s regenerative receiver IC using InP/InGaAs double-heterostructure bipolar transistors

  • Author

    Sano, E. ; Kurishima, K. ; Yamahata, S.

  • Author_Institution
    NTT Syst. Electron. Labs., Atsugi, Japan
  • Volume
    33
  • Issue
    2
  • fYear
    1997
  • fDate
    1/16/1997 12:00:00 AM
  • Firstpage
    159
  • Lastpage
    160
  • Abstract
    A regenerative receiver IC, constructed with a preamplifier, post-amplifier automatic offset controller, PLL-based timing recovery circuit, and D-type flipflop, has been successfully fabricated. 20 Gbit/s error-free operation for an input dynamic range of 13 dB was achieved with a power dissipation of 0.6 W
  • Keywords
    III-V semiconductors; gallium arsenide; heterojunction bipolar transistors; indium compounds; integrated optoelectronics; optical receivers; 0.6 W; 20 Gbit/s; D-type flipflop; InP-InGaAs; InP/InGaAs double-heterostructure bipolar transistor; PLL timing recovery circuit; post-amplifier automatic offset controller; preamplifier; regenerative receiver IC;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19970101
  • Filename
    579512
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1535890