A 40-Gb/s integrated clock and data recovery circuit in a 50-GHz f _T silicon bipolar technology

Author

Wurzer, Martin ; Böck, Josef ; Knapp, Herbert ; Zirwas, Wolfgang ; Schumann, Fritz ; Felder, Alfred

Author_Institution

Corp. Technol., Siemens AG, Munich, Germany

Volume

34

Issue

9

fYear

1999

fDate

9/1/1999 12:00:00 AM

Firstpage

1320

Lastpage

1324

Abstract

Clock and data recovery (CDR) circuits are key electronic components in future optical broadband communication systems. In this paper, we present a 40-Gb/s integrated CDR circuit applying a phase-locked loop technique. The IC has been fabricated in a 50-GHz f _T self-aligned double-polysilicon bipolar technology using only production-like process steps. The achieved data rate is a record value for silicon and comparable with the best results for this type of circuit realized in SiGe and III-V technologies

Keywords

bipolar digital integrated circuits; digital communication; digital phase locked loops; elemental semiconductors; high-speed integrated circuits; optical communication equipment; silicon; synchronisation; 40 Gbit/s; 50 GHz; PLL technique; Si; Si bipolar technology; integrated clock/data recovery circuit; optical broadband communication systems; phase-locked loop technique; self-aligned double-polysilicon technology; Bipolar integrated circuits; Broadband communication; Clocks; Electronic components; Germanium silicon alloys; Integrated circuit technology; Optical devices; Optical recording; Phase locked loops; Silicon germanium;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.782092

Filename

782092

A 40-Gb/s integrated clock and data recovery circuit in a 50-GHz f T silicon bipolar technology

Wurzer, Martin ; Böck, Josef ; Knapp, Herbert ; Zirwas, Wolfgang ; Schumann, Fritz ; Felder, Alfred

jour

A 40-Gb/s integrated clock and data recovery circuit in a 50-GHz f _T silicon bipolar technology