A fault-tolerant GaAs/CMOS interconnection network for scalable multiprocessors

Author

Butner, steven E. ; Bordelon, Scott L. ; Endres, Lisa ; Dodd, James ; Shetler, Joy

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA

Volume

26

Issue

5

fYear

1991

fDate

5/1/1991 12:00:00 AM

Firstpage

692

Lastpage

705

Abstract

The design of an interconnection network (ICN) for a scalable multiprocessor system is presented. The tree-structured network (called SHUNT for scalable hierarchical unidirectional network topology) is organized so that it can be scaled not only in width (through the use of bit slicing), but also in number of ports and in data transfer speed. The network is made from three custom chip types: cluster controller, crossbar switch, and network interface. Implementation of the first prototype chips in 2-μm CMOS is discussed, and the results of detailed circuit simulations for GaAs implementations are given. The network is fault tolerant and is able to detect and correct all single-bit transmission errors. In addition, it can detect failures and reconfigure to work around problems in controllers, port interfaces, or user processors. The network is part of the experimental decoupled computer architect project (DART) currently under study and development

Keywords

CMOS integrated circuits; III-V semiconductors; application specific integrated circuits; digital integrated circuits; error correction; error detection; fault tolerant computing; gallium arsenide; multiprocessor interconnection networks; 2 micron; ASIC; CMOS interconnection network; DART; GaAs; SHUNT; bit slicing; cluster controller; crossbar switch; custom chip; decoupled computer architect project; fault-tolerant; monolithic IC; network interface; scalable hierarchical unidirectional network topology; scalable multiprocessor system; single-bit transmission errors; tree-structured network; Circuit simulation; Electrical fault detection; Fault tolerance; Gallium arsenide; Multiprocessing systems; Multiprocessor interconnection networks; Network interfaces; Network topology; Switches; Virtual prototyping;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.78240

Filename

78240