Synchronous-mode evaluation of delays in CMOS structures

Author

Deschacht, D. ; Robert, M. ; Auvergne, Daniel

Author_Institution

Lab. d´´Autom. et de Microelectron, de Montpellier, Univ, des Sci. et Tech. du Languedoc, France

Volume

26

Issue

5

fYear

1991

fDate

5/1/1991 12:00:00 AM

Firstpage

789

Lastpage

795

Abstract

The extension of the explicit formulation of delays in CMOS VLSI to synchronous-mode evaluation allows the accurate evaluation of data path timing (few percent with respect to SPICE simulation) of general CMOS structures for all available input drive configurations, resulting in fast identification of timing problems. A validation of this method has been done using general series parallel networks. It was shown to be sufficiently accurate for resolving race problems. An implementation of the proposed algorithms has been conceived as a preprocessor for an event-driven switch simulator and it has been shown to be fast enough for use in VLSI timing analysis

Keywords

CMOS integrated circuits; VLSI; delays; integrated logic circuits; logic testing; CMOS VLSI; CMOS structures; VLSI timing analysis; data path timing; delays; event-driven switch simulator; preprocessor; race problems; synchronous-mode evaluation; timing problem identification; Circuit simulation; Data analysis; Helium; Inverters; Logic circuits; Predictive models; Propagation delay; SPICE; Timing; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.78250

Filename

78250