A single-chip pipelined 2-D FIR filter using residue arithmetic

Novel circuits and architecture for residue arithmetic are presented. These circuits are designed for fast and area-efficient single-chip implementation of digital signal processors. This has been achieved by following an algorithmic approach as opposed to the conventional look-up table approach. Substantial area savings have resulted. The circuits include a residue adder, residue multiplier, binary-to-residue converter, and residue-to-binary converter. Based on these circuits, a prototype single-chip, 3×3, finite impulse response (FIR), variable coefficient, linear phase filter has been designed and fabricated in standard 2-μm CMOS technology. The filter has a pipelined architecture to increase the throughput. Testability in the form of scan-path registers has been incorporated. An interesting feature of this combination is the possible tradeoff available between the precision of the filter coefficients and the image data. The chip has a die size of 6.6×4.2 mm², dissipates 220 mW of power, and is synchronized with a 180-ns clock cycle