A 10-b 15-MHz CMOS recycling two-step A/D converter

A two-step recycling technique is applied to implement a 10-b CMOS analog-to-digital (A/D) converter with a video conversion rate of 15 Msample/s. In a prototype digitally corrected converter, one capacitor-array multiplying digital-to-analog converter (MDAC) is used repeatedly as a sample-and-hold (S/H) amplifier, a DAC, and a residue amplifier so that the proposed converter may obtain linearity with the capacitor-array matching. An experimental fully differential A/D converter implemented using a double-poly 1-μm CMOS technology consumes 250 mW with a 5-V single supply, and its active die area, including all digital logic and output buffers, is 1.75 mm² (2700 mil²). Because the conversion accuracy of the proposed architecture relies on a capacitor-array MDAC linearity, high-resolution CMOS A/D conversions are feasible at high frequencies if sophisticated circuit techniques are further developed. For high-speed two-phase versions, the system can be easily modified to use multiplexing and/or pipelining techniques with a separate S/H amplifier and/or two separate flash converters