A 10-b 50-MHz CMOS D/A converter with 75-Ω buffer

Author

Pelgrom, Marcel J M

Author_Institution

Philips Res. Lab., Eindhoven, Netherlands

Volume

25

Issue

6

fYear

1990

fDate

12/1/1990 12:00:00 AM

Firstpage

1347

Lastpage

1352

Abstract

A 10-b 50-MHz digital-to-analog (D/A) converter for video applications that is based on a dual-ladder resistor string is presented. This approach allows the linearity requirements to be met without the need for selection or trimming. The D/A decoding scheme reduces the glitch energy, and signal-dependent switch signals reduce high-frequency distortion. The output buffer allows driving 1 V_pp to 75 Ω. The chip consumes 65 mW at maximum clock frequency and a full-swing output signal. The device is processed in a standard 1.6-μm CMOS process with a single 5-V supply voltage. The double-ladder architecture allows the requirements for small cell area and high linearity to be separated. Compensation techniques have been applied to reduce the second- and third-order distortion components; at 5-MHz signal frequency the total harmonic distortion is -53 dB

Keywords

CMOS integrated circuits; decoding; digital-analogue conversion; ladder networks; 5 MHz; CMOS process; D/A converter; D/A decoding scheme; double-ladder architecture; dual-ladder resistor string; full-swing output signal; glitch energy; high-frequency distortion; linearity; maximum clock frequency; output buffer; second-order distortion; signal-dependent switch signals; small cell area; third-order distortion components; total harmonic distortion; video applications; Current supplies; Decoding; Distortion; Linearity; Matrix converters; Power supplies; Resistors; Switches; Transmission line matrix methods; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.62178

Filename

62178