A single-flux-quantum demultiplexer

Author

Miller, D.L. ; Przybysz, J.X. ; Worsham, A.H. ; Joonhee Kang

Author_Institution

Northrop-Grumman Sci. & Technol. Center, Pittsburgh, PA, USA

Volume

7

Issue

2

fYear

1997

fDate

6/1/1997 12:00:00 AM

Firstpage

2690

Lastpage

2692

Abstract

Many applications of Single-Flux-Quantum (SFQ) circuits will rely on the transfer of multi-Gigabit per second data streams from SFQ logic to semiconductor logic for further processing. The low output voltages of superconducting circuits currently limit the data rate per channel to a few GHz. We have designed and fabricated an SFQ demultiplexer to reduce data transfer clock rates. The demultiplexer uses clocked data distribution through a binary tree architecture. The circuit was fabricated using an eight level Nb/AlO/sub x//Nb process and tested at 4.2 K.

Keywords

aluminium compounds; demultiplexing equipment; niobium; superconducting logic circuits; superconductor-insulator-superconductor devices; 4.2 K; Nb-AlO-Nb; SFQ logic; binary tree architecture; clocked data distribution; data transfer clock rates; eight level Nb/AlO/sub x//Nb process; single-flux-quantum demultiplexer; superconducting circuits; Binary trees; Circuit testing; Clocks; Frequency; Logic circuits; Low voltage; Niobium; Shift registers; Superconducting logic circuits; Timing;

fLanguage

English

Journal_Title

Applied Superconductivity, IEEE Transactions on

Publisher

ieee

ISSN

1051-8223

Type

jour

DOI

10.1109/77.621793

Filename

621793