Impact of size effects in local interconnects for future technology nodes: A study based on full-chip layouts

Author

Ceyhan, Ahmet ; Moongon Jung ; Panth, Shreepad ; Sung Kyu Lim ; Naeemi, Azad

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2014

fDate

20-23 May 2014

Firstpage

345

Lastpage

348

Abstract

In this paper, we investigate the impact of local interconnect size effects on the performance of integrated circuits (ICs) based on timing-closed GDSII-level layouts of circuit blocks with detailed routing. For this purpose, we create multiple standard cell and interconnect libraries for 45-, 22-, 11- and 7-nm technology nodes considering scaling trends projected by the International Technology Roadmap for Semiconductors (ITRS) and assuming various sets of size effect parameters. We make comparisons between the performances of circuit designs that are implemented using these libraries.

Keywords

integrated circuit interconnections; integrated circuit layout; size effect; GDSII-level layouts; circuit designs; full-chip layouts; integrated circuits; interconnect libraries; local interconnects; size 11 nm; size 22 nm; size 45 nm; size 7 nm; size effects; Conductivity; Integrated circuit interconnections; Libraries; Parity check codes; Routing; Standards; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC), 2014 IEEE International

Conference_Location

San Jose, CA

Print_ISBN

978-1-4799-5016-4

Type

conf

DOI

10.1109/IITC.2014.6831831

Filename

6831831