A 100-MHz 64-tap FIR digital filter in 0.8-μm BiCMOS gate array

Author

Yoshino, Toshiaki ; Jain, Rajeev ; Yang, Paul T. ; Davis, Harvey ; Gass, Wanda ; SHAH, ASHWIN H.

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

Volume

25

Issue

6

fYear

1990

fDate

12/1/1990 12:00:00 AM

Firstpage

1494

Lastpage

1501

Abstract

A 64-tap FIR (finite impulse response) digital filter that has been designed using a newly developed filter compiler and fabricated in a 0.8-μm triple-level interconnect BiCMOS gate array technology is presented. The filter has been tested and is fully functional at a 100-MHz clock rate. These results are obtained by combining an optimized architecture and gate array floorplan with submicrometer BiCMOS technology. The filter occupies 49 mm², which is approximately two-thirds of the 100 K gate array core. The design uses an equivalent of 55 K gates (two-input NAND gates). The device input/output are 100 K emitter-coupled-logic (ECL) compatible

Keywords

BIMOS integrated circuits; circuit layout CAD; digital filters; digital integrated circuits; logic CAD; logic arrays; 0.8 micron; 100 MHz; BiCMOS gate array; CAD; ECL compatible outputs; FIR digital filter; filter compiler; finite impulse response; gate array; optimized architecture; submicron technology; triple-level interconnect; two-input NAND gates; BiCMOS integrated circuits; Clocks; Digital filters; Finite impulse response filter; Frequency domain analysis; Instruments; Laboratories; Prototypes; Testing; Throughput;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.62185

Filename

62185