Design of multilevel interconnect network of an ASIC macrocell for 7.5nm technology node using carbon based interconnects

Author

Farahani, Esmat Kishani ; Sarvari, Reza

Author_Institution

Dept. of Electr. Eng., Sharif Univ. of Technol., Tehran, Iran

fYear

2014

fDate

20-23 May 2014

Firstpage

163

Lastpage

166

Abstract

Multilevel interconnect network of a macrocell for 7.5 nm technology node is designed with carbon based interconnects (CBI) and Cu. Results are compared. Constrains of using CBI is discussed. It is shown that by using CBI power dissipation associated with wires could decrease by 32%. To use GNRs for more than one metal pair, reverse wire pitch idea is proposed that prevents undesirable increase in the number of metal layers.

Keywords

application specific integrated circuits; carbon; copper; integrated circuit design; integrated circuit interconnections; wires (electric); ASIC macrocell; C; CBI power dissipation; Cu; carbon based interconnects; metal layers; multilevel interconnect network; reverse wire pitch; size 7.5 nm; Computer aided software engineering; Delays; Logic gates; Macrocell networks; Metals; Power dissipation; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC), 2014 IEEE International

Conference_Location

San Jose, CA

Print_ISBN

978-1-4799-5016-4

Type

conf

DOI

10.1109/IITC.2014.6831853

Filename

6831853

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=154213