DocumentCode
1545289
Title
A multigigabit DRAM technology with 6F2 open-bitline cell, distributed overdriven sensing, and stacked-flash fuse
Author
Takahashi, Tsugio ; Sekiguchi, Tomonori ; Takemura, Riichiro ; Narui, Seiji ; Fujisawa, Hiroki ; Miyatake, Shinichi ; Morino, Makoto ; Arai, Koji ; Yamada, Satoru ; Shukuri, Shoji ; Nakamura, Masayuki ; Tadaki, Yoshitaka ; Kajigaya, Kazuhiko ; Kimura, Kat
Author_Institution
Elpida Memory Inc., Kanagawa, Japan
Volume
36
Issue
11
fYear
2001
fDate
11/1/2001 12:00:00 AM
Firstpage
1721
Lastpage
1727
Abstract
A multigigabit DRAM technology was developed that features a low-noise 6F2 open-bitline cell with fully utilized edge arrays, distributed overdriven sensing for operation below 1 V, and a highly reliable post-packaging repair scheme using a stacked-flash fuse. This technology, which can be used to fabricate a 0,13-μm 180-mm2 1-Gb DRAM assembled in a 400-mil package, was verified using a 57.6-mm2, 200-MHz array-cycle, 256-Mb test chip with 0.109-μm2 cells
Keywords
CMOS memory circuits; DRAM chips; chip-on-board packaging; high-speed integrated circuits; integrated circuit noise; low-power electronics; 1 Gbit; 256 Mbit; COB; distributed overdriven sensing; fully utilized edge arrays; high-speed; low-noise open-bitline cell; multigigabit DRAM technology; reliable post-packaging repair; stacked-flash fuse; Assembly; Associate members; Fuses; Lead compounds; Low voltage; Packaging; Random access memory; Semiconductor device noise; Testing; Timing;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.962294
Filename
962294
Link To Document