Modeling and electrical analysis of seamless high off-chip connectivity (SHOCC) interconnects

Author

Afonso, Sergio ; Schaper, Leonard W. ; Parkerson, James P. ; Brown, William D. ; Ang, Simon S. ; Naseem, Hameed A.

Author_Institution

Microswitch Honeywell Inc., Richardson, TX, USA

Volume

22

Issue

3

fYear

1999

fDate

8/1/1999 12:00:00 AM

Firstpage

309

Lastpage

320

Abstract

Scaling down on-chip interconnect cross-sectional dimensions results not only in higher circuit wiring density, but also in the long lossy line problem, wherein the long lines become highly resistive and have unacceptable delays. One possible solution to the problem of long lossy lines is to transfer these lines off-chip using seamless high off-chip connectivity (SHOCC) technology. In this work, me modeled and studied the electrical performance of SHOCC signal lines. The performance of SHOCC interconnects was compared with that of typical on-chip interconnerts. Modeling and simulation results, along with recommendations with regards to driver sizes and the type of interconnect that should be used, are presented

Keywords

integrated circuit interconnections; integrated circuit modelling; RC delay; SHOCC interconnect; electrical analysis; lossy transmission line; seamless high off-chip connectivity interconnect; simulation model; Central Processing Unit; Clocks; Copper; Delay; Flip chip; High speed integrated circuits; Integrated circuit interconnections; Performance loss; Predictive models; Wiring;

fLanguage

English

Journal_Title

Advanced Packaging, IEEE Transactions on

Publisher

ieee

ISSN

1521-3323

Type

jour

DOI

10.1109/6040.784478

Filename

784478