SRAM cell stability under the influence of parasitic resistances and data holding voltage as a stability prober

Author

Kato, H. ; Matsui, M. ; Sato, K. ; Shibata, H. ; Hashimoto, K. ; Ootani, T. ; Ochii, K.

Author_Institution

Hakodate Nat. Coll. of Technol., Japan

Volume

32

Issue

2

fYear

1997

fDate

2/1/1997 12:00:00 AM

Firstpage

232

Lastpage

237

Abstract

The reliability and performance of SRAM are highly dependent on the cell stability, and the stability is affected by parasitic resistances in a memory array. The parasitic resistances result in a correlative behavior of the cells and are difficult to analyze and measure in a memory array. This topic has been rarely discussed in the literature. In this paper, the correlative behavior is analyzed by trajectories in a phase diagram composed by cell storage nodes. Electrical probing is done by the data holding test. The validity of the analysis and the probing method is confirmed by the measurements on a 0.8-μm 1-Mb CMOS SRAM. An aspect of the cell scaling with attention to the parasitic resistance is also discussed

Keywords

CMOS memory circuits; SRAM chips; VLSI; circuit stability; electric resistance; integrated circuit reliability; 0.8 micron; 1 Mbit; CMOS SRAM; SRAM cell stability; cell scaling; cell storage nodes; data holding test; data holding voltage; electrical probing; memory array; parasitic resistances; reliability; stability prober; static RAM; Circuit stability; Electric resistance; Electrical resistance measurement; Equivalent circuits; Geometry; Helium; Random access memory; Testing; Very large scale integration; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.551915

Filename

551915