A bipolar low-voltage quarter-square multiplier with a resistive-input based on the bias offset technique

Author

Kimura, Katsuji

Author_Institution

Fundamental Technol. Dev. Dept.-I, NEC Corp., Yokohama, Japan

Volume

32

Issue

2

fYear

1997

fDate

2/1/1997 12:00:00 AM

Firstpage

258

Lastpage

266

Abstract

A bipolar low-voltage quarter-square multiplier is presented. The proposed multiplier is very simple because the multiplier cell is built from four identical emitter-coupled pairs connected in parallel and its input system is realized using resistive dividers. Therefore, it is also very practical because it is easy to implement the circuit on a large scale integration (LSI). The fundamental characteristics at a 1 V supply voltage were verified on a breadboard using transistor-arrays and discrete components, it is, furthermore, very suitable for low-power operation

Keywords

analogue multipliers; bipolar analogue integrated circuits; large scale integration; 1 V; LSI; LV quarter-square multiplier; bias offset technique; bipolar low-voltage multiplier; emitter-coupled pairs; large scale integration; low-power operation; resistive dividers; resistive-input; Circuits; Data communication; Demodulation; Frequency modulation; Information processing; Large scale integration; Low voltage; Signal processing; Temperature; Transconductance;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.551920

Filename

551920