Reliable tantalum-gate fully-depleted-SOI MOSFET technology featuring low-temperature processing

Author

Ushiki, Takeo ; Yu, Mo-Chiun ; Hirano, Yuichi ; Shimada, Hisayuki ; Morita, Mizuho ; Ohmi, Tadahiro

Author_Institution

Tohoku Univ., Sendai, Japan

Volume

44

Issue

9

fYear

1997

fDate

9/1/1997 12:00:00 AM

Firstpage

1467

Lastpage

1472

Abstract

A reliable tantalum (Ta)-gate device technology, which can drastically reduce the number of process steps, has been developed. Ta-gate fully-depleted-silicon-on-insulator (FDSOI) MOSFETs with 0.15-μm gate length by low-temperature processing below 500°C after the gate oxide formation have good on/off characteristics. Comprehensive design guidelines for Ta-gate MOSFETs in the deep-submicrometer regime is provided by investigating a wide range of performance and reliability constraints on the process temperature and the SOI thickness. In the guideline, the recrystallization of the source/drain region gives inferior limits of the SOI thickness and the process temperature. Thermal reaction between Ta and SiO₂ films sets a superior limit of the process temperature, and a short-channel effect sets a superior limit of the SOI thickness

Keywords

CMOS integrated circuits; MOSFET; ULSI; integrated circuit design; integrated circuit reliability; leakage currents; silicon-on-insulator; 0.15 micron; deep-submicrometer regime; fully-depleted-SOI MOSFET; low-temperature processing; on/off characteristics; process temperature; reliability constraints; short-channel effect; source/drain region recrystallisation; thermal reaction; Doping; Guidelines; Impurities; MOSFET circuits; Performance loss; Plasma temperature; Temperature distribution; Thickness control; Threshold voltage; Voltage control;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.622603

Filename

622603