DocumentCode
1548356
Title
A single-chip MPEG2 MP@HL decoder for DTV recording/playback systems
Author
Watanabe, Y. ; Otobe, Y. ; Yoshitomi, K. ; Takahashi, H. ; Kohiyana, K.
Author_Institution
Fujitsu Labs. Ltd., Kawasaki, Japan
Volume
47
Issue
3
fYear
2001
fDate
8/1/2001 12:00:00 AM
Firstpage
405
Lastpage
411
Abstract
This paper presents an MPEG2 MP@HL decoder LSI for use in digital TV (DTV) recording/playback systems such as a home server. It integrates the functions required in home servers on a single chip. The chip incorporates not only basic functions for image processing but also effective functions for stream recording/playback. It enables smooth execution of trick plays without complex operations in an external CPU, and makes it easy to build recording/playback systems
Keywords
CMOS digital integrated circuits; decoding; digital signal processing chips; digital television; large scale integration; video recording; video servers; video signal processing; DTV recording/playback systems; LSI; digital TV; home server; image processing; single-chip MPEG2 MP@HL decoder; stream recording/playback; trick play; Control systems; Decoding; Digital TV; Digital video broadcasting; Graphics; Image processing; Large scale integration; SDRAM; Streaming media; TV broadcasting;
fLanguage
English
Journal_Title
Consumer Electronics, IEEE Transactions on
Publisher
ieee
ISSN
0098-3063
Type
jour
DOI
10.1109/30.964127
Filename
964127
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