Analysis and improvement of the noise immunity in a single-chip super-regenerative transceiver

The authors present a methodology for rapid verification of substrate noise problems in a single-chip transceiver. The procedure allows knowing, with reasonable accuracy, how much isolation is obtained between parasitic and sensitive blocks without taking into account all the irrelevant details. The analysis of the noise coupling problem is therefore greatly accelerated allowing verification of a large variety of isolation strategies. The procedure is illustrated on a single-chip BiCMOS super-regenerative transceiver dedicated to ISM applications. Techniques allowing a reduction of the noise injection in the substrate by the different noisy parts of the circuit are also presented