DocumentCode
1550208
Title
Efficient method for simulating time delays of distributed interconnections in VLSI circuits
Author
Maffezzoni, P. ; Brambilla, A.
Author_Institution
Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
Volume
35
Issue
12
fYear
1999
fDate
6/10/1999 12:00:00 AM
Firstpage
976
Lastpage
977
Abstract
A new technique is described for modelling a general distributed RC line through a simple lumped net. This reduced order model approximates both the long time voltage response and the input loading effect of the line. The proposed method has the advantage of allowing the employment of circuit simulators such as SPICE to evaluate interconnect delays in complex layouts
Keywords
RC circuits; SPICE; VLSI; circuit simulation; delays; equivalent circuits; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; SPICE; VLSI circuits; circuit simulators; distributed interconnections; general distributed RC line; input loading effect; interconnect delays; lumped net; reduced order model; time delays; time voltage response;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19990702
Filename
788053
Link To Document