DocumentCode
1557010
Title
A Fast-Response Pseudo-PWM Buck Converter With PLL-Based Hysteresis Control
Author
Zheng, Yanqi ; Chen, Hua ; Leung, Ka Nang
Author_Institution
Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin, China
Volume
20
Issue
7
fYear
2012
fDate
7/1/2012 12:00:00 AM
Firstpage
1167
Lastpage
1174
Abstract
Hysteresis voltage-mode control is a simple and fast control scheme for switched-mode power converters. However, it is well-known that the switching frequency of a switched-mode power converter with hysteresis control depends on many factors such as loading current and delay of the controller which vary from time to time. It results in a wide noise spectrum and leads to difficulty in shielding electro-magnetic interference. In this work, a phase-lock loop (PLL) is utilized to control the hysteresis level of the comparator used in the controller, while not interfering with the intrinsic behavior of the hysteresis controller. Some design techniques are used to solve the integration problem and to improve the settling speed of the PLL. Moreover, different control modes are implemented. A buck converter with proposed control scheme is fabricated using a commercial 0.35-μ m CMOS technology. The chip area is 1900 μm × 2200 μm. The switching frequency is locked to 1 MHz, and the measured frequency deviation is within ±1%. The measured load transient response between 160 and 360 mA is 5 μ s only.
Keywords
PWM power convertors; comparators (circuits); delays; electromagnetic interference; electromagnetic shielding; phase locked loops; voltage control; CMOS technology; PLL-based hysteresis control; comparator; control scheme; fast-response pseudo-PWM buck converter; frequency 1 MHz; hysteresis controller; hysteresis level; hysteresis voltage-mode control; phase-lock loop; shielding electro-magnetic interference; size 0.35 mum; switched-mode power converters; switching frequency; wide noise spectrum; Hysteresis; Loading; Phase locked loops; Switches; Switching frequency; Voltage control; Buck converter; hysteresis control; phase-locked loop (PLL);
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2011.2156437
Filename
5887437
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