Charge-mode parallel architecture for vector-matrix multiplication

Author

Genov, Roman ; Cauwenberghs, Gert

Author_Institution

Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA

Volume

48

Issue

10

fYear

2001

fDate

10/1/2001 12:00:00 AM

Firstpage

930

Lastpage

936

Abstract

An internally analog, externally digital architecture for parallel vector-matrix multiplication is presented. A three-transistor unit cell combines a single-bit dynamic random-access memory and a charge injection device binary multiplier and analog accumulator. Digital multiplication of variable resolution is obtained with bit-serial inputs and bit-parallel storage of matrix elements, by combining quantized outputs from multiple rows of cells over time. A prototype 512×128 vector-matrix multiplier on a single 3 mm ×3 mm chip fabricated in standard 0.5-μm CMOS technology achieves 8-bit effective resolution and dissipates 0.5 pJ per multiply-accumulate

Keywords

CMOS analogue integrated circuits; VLSI; analogue multipliers; mixed analogue-digital integrated circuits; parallel architectures; vector quantisation; ADC; CMOS technology; VLSI implementation; analog accumulator; analog array processors; charge injection device binary multiplier; charge-mode parallel architecture; digital multiplication; internally analog externally digital architecture; mixed-signal array architecture; parallel vector-matrix multiplication; row-parallel flash A/D conversion; single-bit DRAM; support vector machines; three-transistor unit cell; vector quantization; CMOS technology; Charge coupled devices; Computer vision; Concurrent computing; Machine vision; Parallel architectures; Random access memory; Support vector machines; Throughput; Very large scale integration;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.974781

Filename

974781