• DocumentCode
    1559551
  • Title

    Improving SoC design quality through a reproducible design flow

  • Author

    Magarshack, Philippe

  • Author_Institution
    STMicroelectronics, Crolles, France
  • Volume
    19
  • Issue
    1
  • fYear
    2002
  • Firstpage
    76
  • Lastpage
    83
  • Abstract
    The author examines the dynamics of system-on-a-chip design and addresses the fundamental question of whether there is a reproducible process for achieving the right design at the right time
  • Keywords
    network synthesis; reproducible design flow; system-on-chip design; Bluetooth; CMOS process; Cellular phones; Costs; Delay effects; Digital signal processing chips; GSM; Microcontrollers; Radio frequency; System-on-a-chip;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.980055
  • Filename
    980055
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1559551