A fast-serial finite field multiplier without increasing the number of registers

In this paper, an efficient architecture for the finite field multiplier is proposed. As conventional LFSR (Linear Feedback Shift Registers) architecture need as many registers as speedup factor, the proposed architecture can achieve fast multiplication without increasing the number of registers by sharing the result register for even and odd bits. Modular cells are designed for easy implementation of the multiplier. The experimental results show that the proposed multiplier is 2 times faster than the serial LFSR multiplier with the same number of registers. The low power feature of the proposed multiplier has a big advantage for power critical application including smart card cryptography processors.