Macromodel for short circuit power dissipation of submicron CMOS inverters and its application to design CMOS buffers

Author

Ulman, S.

Author_Institution

Dept. of Phys., Goa Univ., India

Volume

5

fYear

2003

Abstract

The paper presents a physical and scalable macromodel of submicron CMOS inverters for short circuit power estimation. The macromodel, which is based on the equivalent capacitance concept, can be used to directly compare the short circuit power dissipation and dynamic power dissipation. The validity of the model is estimated by comparing it with the simulated values (SPICE level 3 model). The macromodel is useful in power and delay optimization of a CMOS buffer chain.

Keywords

CMOS logic circuits; buffer circuits; circuit optimisation; circuit simulation; integrated circuit design; integrated circuit modelling; logic design; logic gates; logic simulation; CMOS buffer chain; CMOS inverters; delay optimization; dynamic power dissipation; equivalent capacitance concept; physical scalable macromodel; power estimation; power optimization; short circuit power dissipation; submicron CMOS inverter macromodel; CMOS technology; Capacitance; Geometry; Inverters; MOSFET circuits; Power MOSFET; Power dissipation; Semiconductor device modeling; Solid modeling; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1206250

Filename

1206250