Clock recovery in high-speed multilevel serial links

This paper introduces a simple and hardware efficient clock recovery method for high speed serial links and compares its performance with conventional techniques. Conventional methods are conceptually complex and difficult to realize since they rely on data transitions to recover the clock by oversampling the received signal. In contrast, the new method monitors one or more signal levels and aligns the clock sampling phase with the maximum vertical data eye opening by using the minimum mean squared error algorithm. Besides being easily implementable in a standard CMOS technology, this new method requires only baud rate sampling and is independent of the data transition density. Behavioral simulations predict superior performance of this method compared to a conventional bang bang phase detector based architecture.